| 摘要 |
PROBLEM TO BE SOLVED: To provide an address control circuit which is reduced in circuit size and can perform high-speed operation. SOLUTION: The device is equipped with a first counter 11a and a second counter 11b. Based on a switching signal SS for switching whether an address for memory 3 is incremented by an external clock CLK and externally, a first counter 11a generates a first address signal AD1 by counting a first input signal I1. Based on the clock CLK, the switching signal SS, and the first address signal AD1, a second counter 11b generates a second address signal AD2 by counting a second input signal I2. COPYRIGHT: (C)2005,JPO&NCIPI
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