发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 In a memory array comprising memory cells employing a memory circuit STC and a comparison circuit CP, any one of source and drain electrodes of a transistor having a gate electrode being connected with a search line among a plurality of transistors constituting the comparison circuit CP is connected with a match line HMLr being precharged with a high voltage. A match line decision circuit MDr is arranged in a match line LMLr being precharged with a low voltage and a comparison signal voltage generated in that match line is discriminated depending on the comparison results of information. With such arrangement and operation of a memory array, comparison operation can be carried out at high speed with low power while avoiding the effect of search line driving noise in a pair of match lines. A low power content addressable memory capable of performing search operation at high speed can thereby be realized.
申请公布号 WO2005050663(A1) 申请公布日期 2005.06.02
申请号 WO2003JP14901 申请日期 2003.11.21
申请人 HITACHI, LTD.;ELPIDA MEMORY, INC.;HANZAWA, SATORU;SHIGETA, JUNJI;KIMURA, SHINICHIRO;SAKATA, TAKESHI;TAKEMURA, RIICHIRO;KAJIGAYA, KAZUHIKO 发明人 HANZAWA, SATORU;SHIGETA, JUNJI;KIMURA, SHINICHIRO;SAKATA, TAKESHI;TAKEMURA, RIICHIRO;KAJIGAYA, KAZUHIKO
分类号 G11C15/04 主分类号 G11C15/04
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