发明名称 Diversity receiving apparatus that prevents judgement errors during decoding and a clock generating circuit for a diversity circuit that prevents judgement errors during decoding
摘要 A diversity receiving apparatus separately weights reception signals of a plurality of reception systems using combining coefficients based on a respective amplitude component of each reception signal and combines the weighted reception signals. The diversity receiving apparatus extracts symbol sections in the combined reception signals, and generates a clock for detecting symbols. The diversity receiving apparatus includes a converting unit 314 for uniformly multiplying the combining coefficients if every combining coefficient is below a predetermined threshold and I component ROMs, Q component ROMs, an I component adder 325 and a Q component adder 326 that combine the reception signals using the multiplied combining coefficients.
申请公布号 US6901124(B1) 申请公布日期 2005.05.31
申请号 US20010857184 申请日期 2001.06.19
申请人 SANYO ELECTRIC CO., LTD. 发明人 IINUMA TOSHINORI
分类号 H04B7/08;H04L1/06;H04L7/033;(IPC1-7):H04L1/02 主分类号 H04B7/08
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