发明名称 Method for fabricating a chip scale package using wafer level processing
摘要 Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.
申请公布号 US6900079(B2) 申请公布日期 2005.05.31
申请号 US20030624833 申请日期 2003.07.22
申请人 MICRON TECHNOLOGY, INC. 发明人 KINSMAN LARRY D.;AKRAM SALMAN
分类号 H01L21/56;H01L21/60;H01L29/06;(IPC1-7):H01L21/44;H01L21/48;H01L21/50 主分类号 H01L21/56
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