发明名称 |
Integrating chip scale packaging metallization into integrated circuit die structures |
摘要 |
Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described. Another exemplary embodiment illustrated the use of chip-scale processes for interconnecting discrete integrated circuits. |
申请公布号 |
US6900538(B2) |
申请公布日期 |
2005.05.31 |
申请号 |
US20040760434 |
申请日期 |
2004.01.20 |
申请人 |
MICREL, INC. |
发明人 |
ALTER MARTIN;RUMSEY ROBERT |
分类号 |
H01L21/60;H01L23/31;H01L23/485;(IPC1-7):H01L23/48 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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