发明名称 |
High speed software driven emulator comprised of a plurality of emulation processors with a method to allow high speed bulk read/write operation synchronous DRAM while refreshing the memory |
摘要 |
A system and method for bulk transfer to and from the SRAMs in which a starting memory address is latched and is then incremented every clock cycle to generate a new memory address. The addresses are decoded and memory requests are pipelined to the SRAM memory, one every clock cycle. When the memory controller detects transfer of the boundary of a predetermined number of clock cycles or words (e.g. 64 words or four clock cycles) the burst mode of data transfer is stopped and the memory controller waits for a "done" signal before resuming another cycle of the burst transfer mode. The memory controller on detecting a request on this address boundary first does a memory refresh followed by a requested operation; e.g. a continuation of the transfer operation.
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申请公布号 |
US6901359(B1) |
申请公布日期 |
2005.05.31 |
申请号 |
US20000656541 |
申请日期 |
2000.09.06 |
申请人 |
QUICKTURN DESIGN SYSTEMS, INC. |
发明人 |
BEAUSOLEIL WILLIAM F.;COOK R. BRYAN;NG TAK-KWONG;ROTH HELMUT;TANNENBAUM PETER;THOMAS LAWRENCE A.;TOMASSETTI NORTON J. |
分类号 |
G06F9/455;G06F12/00;G06F12/14;G06F13/16;G06F15/00;G06F15/76;G06F17/50;(IPC1-7):G06F9/455 |
主分类号 |
G06F9/455 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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