发明名称 Method of fabricating vertical integrated circuits
摘要 A method for fabricating a vertical integrated circuit is disclosed. Integrated circuits are fabricated on a substrate with layers of predetermined weak and strong bond regions where deconstructed layers of integrated circuits are fabricated at or on the weak bond regions. The layers are then peeled and subsequently bonded to produce a vertical integrated circuit. An arbitrary number of layers can be bonded and stacked in to a separate vertical integrated circuit. Also disclosed are methods of creating edge interconnects and vias through the substrate to form interconnections between layers and devices thereon.
申请公布号 US2005112848(A1) 申请公布日期 2005.05.26
申请号 US20040020753 申请日期 2004.12.23
申请人 REVEO, INC. 发明人 FARIS SADEG M.
分类号 B81C1/00;G01R31/01;H01L21/66;(IPC1-7):H01L21/00;H01L21/76;H01L21/30;H01L21/46 主分类号 B81C1/00
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