| 摘要 |
An interruption control system includes a first input/output interruption controller, a second input/output interruption controller and an interruption status indicating path. The first input/output interruption controller is coupled to a first peripheral device and a south bridge chip, and issues a wake-up signal to the south bridge chip in response to a first interrupt signal asserted by the first peripheral device so as to deactivate a power-saving state of the computer system. The second input/output interruption controller is coupled to a second peripheral device and a north bridge chip, and in response to a second interrupt signal asserted by the second peripheral device, generates a message signaled interrupt. The interruption status indicating path transmits the message signaled interrupt from the second input/output interruption controller to the south bridge chip to have the south bridge chip deactivate the power-saving state of the computer system in response to the message signaled interrupt.
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