| 摘要 |
PROBLEM TO BE SOLVED: To achieve high rate of failure detection while reducing the burden of layout design and preventing an increase in chip size when inserting test points of a semiconductor integrated circuit. SOLUTION: Controllability probability is calculated on the basis of target circuit information (S002). Initial layout is executed according to the circuit information (S003). A wiring pair is extracted from the layout result (S004). Candidates for test points to be inserted are extracted according to the controllability probability and the wiring pair (S005). A determination is made as to whether the candidates exist (S006). When the candidates exist, a test-point insertion position is selected (S007). The circuit arrangement of the test points to be inserted there is selected (S008). The test points of the circuit arrangement are virtually inserted (S009). Circuits inserted with the test points are laid out again (S010). A determination is made as to whether the resulting circuit overhead is within a predetermined range (S011). When it is outside the predetermined range, the number of test points is narrowed down (S012). COPYRIGHT: (C)2005,JPO&NCIPI
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