发明名称 Semiconductor memory device and defect remedying method thereof
摘要 A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. This structure in which the peripheral circuits are arranged at the center portion of the chip permits the longest signal transition paths to be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.
申请公布号 US6898130(B2) 申请公布日期 2005.05.24
申请号 US20030683260 申请日期 2003.10.14
申请人 HITACHI VLSI ENGINEERING CORP. 发明人 KAJIGAYA KAZUHIKO;MIYAZAWA KAZUYUKI;TSUNOZAKI MANABU;OSHIMA KAZUYOSHI;YAMAZAKI TAKASHI;SAKAI YUJI;SAWADA JIRO;YAMAGUCHI YASUNORI;MATSUMOTO TETSUROU;UDO SHINJI;YOSHIOKA HIROSHI;SAITO HIROKAZU;TAKANO MITSUHIRO;MORINO MAKOTO;MIYATAKE SINICHI;MIYAMOTO EIJI;KASAMA YASUHIRO;ENDO AKIRA;HORI RYOICHI;ETOH JUN;HORIGUCHI MASASHI;IKENAGA SHINICHI;KUMATA ATSUSHI
分类号 G11C5/00;G11C5/02;G11C5/06;G11C11/406;H01L23/485;(IPC1-7):G11C16/04 主分类号 G11C5/00
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