发明名称 Machine instruction for enhanced control of multiple virtual processor systems
摘要 A multiple virtual processor (MVP) system using a special "YIELD" machine instruction inserted into a thread (virtual processor) at a selected point to trigger an immediate thread change (i.e., transfer of physical processor control to another thread). When the physical processor processes a YIELD instruction, the task thread surrenders control of the physical processor, and an otherwise idle thread is selected by a thread scheduling mechanism of the MVP system for loading into the physical processor. In one embodiment, the YIELD instruction includes an input operand that identifies the hardware signal on which the issuing thread intends to wait, and a result operand indicating the reason for reactivation.
申请公布号 US2005108711(A1) 申请公布日期 2005.05.19
申请号 US20030714137 申请日期 2003.11.13
申请人 INFINEON TECHNOLOGIES NORTH AMERICA CORPORATION 发明人 ARNOLD ROGER D.;OBER ROBERT E.
分类号 G06F9/30;G06F9/38;G06F9/46;(IPC1-7):G06F9/46 主分类号 G06F9/30
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