Read-out signal enhancement method for memory with passive memory elements using selective inversion of logic level of information bits during information write-in

摘要

The method has the read-out signal enhanced by checking if the logic level applied to more than half of the bit lines (BLi) for the passive memory cells (12-1,12-M,12-S) corresponds to a low-ohmic resistance value for the latter, during write-in of information in the memory (10), for inversion of the logic level of the information bits when this is the case, with generation of an additional test bit (S) representing the logic level of the information bits.