发明名称 |
Apparatus having a micro-instruction queue, a micro-instruction pointer programmable logic array and a micro-operation read only memory and method for use thereof |
摘要 |
Embodiments of the present invention relate to high-performance processors, and more specifically, to processors that store all operation information associated with each instruction in a single memory. A processor including multiple programmable logic arrays (PLAs); an instruction pointer queue coupled to the multiple PLAs; and an instruction pointer sequencing logic/predictor component coupled to the instruction pointer queue. The processor further includes a micro-operation cache coupled to the instruction pointer sequencing logic/predictor component; a micro-operation memory coupled to the micro-operation cache; and a trace pipe (TPIPE) coupled to the micro-operation cache and the instruction pointer queue.
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申请公布号 |
US2005108508(A1) |
申请公布日期 |
2005.05.19 |
申请号 |
US20030714674 |
申请日期 |
2003.11.18 |
申请人 |
INTEL CORPORATION |
发明人 |
HEBDA REBECCA E.;STEPHAN JOURDAN J. |
分类号 |
G06F9/28;G06F9/30;G06F9/38;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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