发明名称 NONBLOCKING AND DETERMINISTIC UNICAST PACKET SCHEDULING
摘要 A system for scheduling unicast packets through an interconnection network, comprising r1, input ports with each input port having r2 input queues, r2 output ports with each output port having r1 output queues, and the interconnection network having a speedup of at least with, Formula (I), subnetworks, and each subnetwork comprising at least one first internal link connected to each input port for a total of at least r1 first internal links, each subnetwork further comprising at least one second internal link connected to each output port for a total of at least r2 second internal links is operated in strictly nonblocking manner in accordance with the invention by scheduling, at most r1 packets in each switching time to be switched in at most r1 switching times when r1 <=r2 and at most r2 packets in each switching time to be switched in at most r1 switching times when r2 <= R1 in deterministic manner, and without the requirement of segmentation and reassembly of packets. The system is also operated at 100% throughput, work conserving, fair, and yet deterministically thereby never congesting the output ports. The system performs only one iteration for arbitration, and with mathematical minimum speedup in the interconnection network. The system operates with absolutely no packet reordering issues, no internal buffering of packets in the interconnection network, and hence in a truly cut-through and distributed manner. In one embodiment, the system is operated in strictly nonblocking manner with only one subnetwork and with double switching rate through the subnetwork. In another embodiment, the system is operated in rearrangeably nonblocking manner with a speedup of at least, Formula (II), in the interconnection network. When the number of input ports r1 is equal to the number of output ports Pi, and r1 = r2 = r , the interconnection network having a speedup of at least, Formula (III), is operated in strictly nonblocking and deterministic manner in accordance with the invention by scheduling at most r packets in each switching time to be switched in at most r switching times. And with a speedup of at least, Formula (IV), in the interconnection network, the system is operated in rear rangeably nonblocking and deterministic manner. The system also offers end to end guaranteed bandwidth and latency for packets from input ports to output ports. In all the embodiments, the interconnection network may be crossbar network, shared memory network, clos network, hypercube network, or any internally nonblocking interconnection network or network of networks.
申请公布号 CA2544219(A1) 申请公布日期 2005.05.19
申请号 CA20042544219 申请日期 2004.10.29
申请人 KONDA, VENKAT 发明人 KONDA, VENKAT
分类号 H04L12/56;G06F;H04L12/46;H04L29/06 主分类号 H04L12/56
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