发明名称 |
Structure and method for lead free solder electronic package interconnections |
摘要 |
An electronic package having a solder interconnect liquidus temperature hierarchy to limit the extent of the melting of the C4 solder interconnect during subsequent second level join/assembly and rework operations. The solder hierarchy employs the use of off-eutectic solder alloys of Sn/Ag and Sn/Cu with a higher liquidus temperature for the C4 first level solder interconnections, and a lower liquidus temperature alloy for the second level interconnections. When the second level chip carrier to PCB join/assembly operations occur, the chip to chip carrier C4 interconnections do not melt completely. They continue to have a certain fraction of solids, and a lower fraction of liquids, than a fully molten alloy. This provides reduced expansion of the solder join and consequently lower stresses on the C4 interconnect.
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申请公布号 |
US2005106059(A1) |
申请公布日期 |
2005.05.19 |
申请号 |
US20040991581 |
申请日期 |
2004.11.18 |
申请人 |
FAROOQ MUKTA G.;INTERRANTE MARIO;SABLINSKI WILLIAM |
发明人 |
FAROOQ MUKTA G.;INTERRANTE MARIO;SABLINSKI WILLIAM |
分类号 |
B23K35/26;C22C13/00;H01L21/56;H01L21/60;H01L21/68;H01L23/31;H01L23/485;H01L23/498;H05K3/28;H05K3/34;(IPC1-7):C22C13/00 |
主分类号 |
B23K35/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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