发明名称 |
Memory module, memory chip, and memory system |
摘要 |
A memory module includes at least one CAR and a plurality of DRAMs provided so as to be close and adjacent to one another on one face and the other face of a module substrate. The DRAMs are divided into a plurality of memory groups. Memory groups adjacent to each other of these memory groups are paired with each other. One of this pair is a 1-ranked memory group and the other is a 2-ranked memory group. This pair of the memory groups is connected to the CAR via short wiring with a T-branch structure having a short stub. One of the pair of the memory groups on the signal-reception side functions as an open end. Active termination is performed by a termination resistor of the other of the pair of the memory groups on the signal-non-reception side. Subsequently, signal reflections can be reduced.
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申请公布号 |
US2005105318(A1) |
申请公布日期 |
2005.05.19 |
申请号 |
US20030699628 |
申请日期 |
2003.10.31 |
申请人 |
FUNABA SEIJI;NISHIO YOJI |
发明人 |
FUNABA SEIJI;NISHIO YOJI |
分类号 |
G06F12/00;G06F12/06;G06F13/00;G06F13/16;G11C5/00;G11C5/06;G11C11/401;(IPC1-7):G11C5/06 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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