发明名称 Semiconductor manufacturing line availability evaluating system and design system
摘要 An availability evaluation system of a semiconductor manufacturing line, comprising a unit configured to calculate an incidence probability Xi (i=1 to k) in combination by applying a tool operation probability and a tool stoppage probability to all combinations "k" in which at least a line fabrication availability is not zero, of the combinations of operation and stoppage of tools, and by obtaining a product of the probabilities of all the tools, and a unit configured to, when a product between the incidence probability Xi of a combination and a fabrication availability Yi of the combination is defined as a probability converted fabrication availability with respect to each of the combinations, calculate an availability value of Q=Sigma<SUB>(i=1 to k)</SUB>X1xY1/F obtained by dividing a sum of probability converted fabrication availabilities of the combinations by a fabrication availability F at a 100% availability.
申请公布号 US2005107904(A1) 申请公布日期 2005.05.19
申请号 US20040948166 申请日期 2004.09.24
申请人 MIKATA YUUICHI 发明人 MIKATA YUUICHI
分类号 G05B19/418;H01L21/00;H01L21/02;(IPC1-7):H01L21/00 主分类号 G05B19/418
代理机构 代理人
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