发明名称 Semiconductor device
摘要 A dummy cell includes a plurality of first memory cells MC for storing "1" or "0", arranged at points of intersection between a plurality of word lines WR 0 to WR 7 and a plurality of first data lines D 0 to D 7, a plurality of first dummy cells MCH for storing "1" or "0", arranged at points of intersection between the word lines WR 0 to WR 7 and a first dummy data line, and a plurality of second dummy cells MCL for storing "0", arranged at points of intersection between the word lines WR 0 to WR 7 and a second dummy data line DD 1.
申请公布号 US2005105326(A1) 申请公布日期 2005.05.19
申请号 US20040009449 申请日期 2004.12.13
申请人 HITACHI, LTD. 发明人 HANZAWA SATORU;SAKATA TAKESHI
分类号 G11C11/15;G11C5/00;G11C7/00;G11C11/00;G11C11/16;G11C11/34;H01L27/22;H01L31/0328;(IPC1-7):G11C11/00 主分类号 G11C11/15
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