| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device changed in synchronous timing by CAS (Column Address Strobe) latency (CL). SOLUTION: This semiconductor memory device is provided with a clock buffer for receiving an external clock signal and CL (CAS latency), and generating a first clock signal synchronized with the rising edge of a clock signal or a second clock signal synchronized with the falling edge of the clock signal based on the CL information, a CSL decoder for receiving and decoding a column selection address, and outputting a decoding address for selecting a column selection line (CSL) in synchronization with the first or second clock signal, a control signal generation circuit for outputting a control signal synchronized with one clock signal in response to one of the first and second clock signals, and a CSL driver for driving the CSL in synchronization with one of the first and second clock signals in response to the decoding address and the control signal. COPYRIGHT: (C)2005,JPO&NCIPI
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