发明名称 TESTING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a simple testing method for a semiconductor integrated circuit dispensing with a great deal of economic burden. SOLUTION: This testing method of a clock synchronization type semiconductor integrated circuit goes through the following steps. Firstly, a capacitor 11 is parallel connected between a power source terminal 10a and a ground terminal 10b of the semiconductor integrated circuit 10 (Step 50). Then, the capacitor 11 is charged by supplying a power source voltage from a power source device 13 to the source terminal 10a (Step 51). The supply of a clock to the integrated circuit 10 is terminated (Step 52) and thereafter the supply of the source voltage is terminated (Step 53). Potential Vsup between the source terminal 10a and the ground terminal 10b is measured after the lapse of a prescribed time period (Step 54). Whether or not an abnormal leak current exists in the integrated circuit 10 is determined based on the level of the potential Vsup (Step 55). COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005127716(A) 申请公布日期 2005.05.19
申请号 JP20030360154 申请日期 2003.10.21
申请人 SANYO ELECTRIC CO LTD 发明人 ARAKI MORIO
分类号 G01R31/26;G01R31/317;(IPC1-7):G01R31/26 主分类号 G01R31/26
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