| 摘要 |
The invention relates to the architecture of high-performance parallel computing systems and discloses a heterogeneous synergetic computing system comprising N functional units and an each-to-each switchboard with L data inputs, M address inputs and M data outputs, with M>=L and one-to-one correspondence between address inputs and data outputs and where at least one of said functional units comprises a control device, an instruction memory and an operational device and having m data inputs, m address outputs and l data outputs, where m<=M and l<=L. The object of the invention is to obtain an extended area of application of such parallel computing systems, to increase the throughput by expanding the stream of data to be processed and to optimize hardware requirements.
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