MULTIPLE CLOCK DOMAIN MICROPROCESSOR

摘要

A multiple clock domain (MCD) microarchitecture (100) uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block (110, 120, 130 and 140) operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. Thus, fully synchronous design practices are used in the design of each domain.