发明名称 |
SEMICONDUCTOR HETEROSTRUCTURES HAVING REDUCED DISLOCATION PILE-UPS AND RELATED METHODS |
摘要 |
Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein. |
申请公布号 |
EP1530800(A2) |
申请公布日期 |
2005.05.18 |
申请号 |
EP20030759202 |
申请日期 |
2003.08.22 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
LEITZ, CHRISTOPHER;VINEIS, CHRISTOPHER;WESTHOFF, RICHARD;YANG, VICKY;CURRIE, MATTHEW |
分类号 |
H01L21/20;C30B25/02;C30B25/18;C30B29/52;H01L21/205;H01L21/302;H01L21/8238;H01L31/0328 |
主分类号 |
H01L21/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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