发明名称 Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide
摘要 A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage. The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer. In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region. This higher-doped pocket of semiconductor material does not totally deplete during device operation. Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region.
申请公布号 US6894349(B2) 申请公布日期 2005.05.17
申请号 US20020104342 申请日期 2002.03.22
申请人 发明人
分类号 H01L21/336;H01L29/06;H01L29/08;H01L29/78;(IPC1-7):H01L29/76 主分类号 H01L21/336
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