发明名称 |
Scannable synchronizer having a deceased resolving time |
摘要 |
The present invention provides a synchronizer for receiving an incoming data signal of a first clock domain and for outputting a data signal of a second clock domain. The synchronizer comprises an input stage, a master latch, a transfer stage and a slave latch. The input stage receives the data signal of the first clock domain and outputs the data signal to the master latch when the input stage is clocked with a master clock signal. The master latch stores the data signal at a storage node of the master latch. The master latch has a resolve time associated with it during which the master latch seeks to resolve the data signal to a logic 0 or a logic 1. The transfer stage transfers the data signal stored in the master latch to the slave latch when the transfer stage is clocked with a slave clock signal.
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申请公布号 |
US6895061(B1) |
申请公布日期 |
2005.05.17 |
申请号 |
US19990426990 |
申请日期 |
1999.10.26 |
申请人 |
AGILENT TECHNOLOGIES, INC. |
发明人 |
STONG GAYVIN E |
分类号 |
H03K3/037;(IPC1-7):H04L7/00 |
主分类号 |
H03K3/037 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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