发明名称 |
Single chip ASIC and compact packaging solution for an avalanche photodiode (APD) and bias circuit |
摘要 |
A compact integrated APD device integrates the bias voltage and temperature compensation functions inside a standard 4-pin PIN package. The active components of the bias and temperature compensation circuits are integrated into a single ASIC using a high-voltage CMOS process and operated at frequencies of at least 1 MHz to greatly reduce the size of the passive components. To mount the relatively large ASIC chip inside the package with the APD chip, TIA chip and passives, the 4-pin package may be modified by either recessing the pins inside the can to facilitate surface mounting the ASIC or adding a spacer inside the can to facilitate three-dimensional packaging. Communication with the bias and temperature circuits is accomplished using a unique bi-directional 1-wire serial interface via the power supply pin. A clock signal is preferably embedded in the control data to synchronize the APD with an external controller.
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申请公布号 |
US6894266(B2) |
申请公布日期 |
2005.05.17 |
申请号 |
US20030367126 |
申请日期 |
2003.02.14 |
申请人 |
OPLINK COMMUNICATIONS, INC. |
发明人 |
RICHARD JENKIN ANGELO;GILLILAND PATRICK B.;CHAMNESS ERIC VAUGHAN;ANGUELOV EVGUENIY DIMITROV |
分类号 |
H01J40/14;(IPC1-7):H01J40/14 |
主分类号 |
H01J40/14 |
代理机构 |
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主权项 |
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地址 |
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