发明名称 |
Networked processor for a pipeline architecture |
摘要 |
A networking application processor is provided. The processor includes an input socket configured to receive data packets. The processor includes a memory for holding instructions and circuitry configured to access data structures associated with the processing stages. The circuitry configured to access data structures enables a single cycle access to an operand from a memory location. An arithmetic logic unit (ALU) is provided. Circuitry for aligning operands to be processed by the ALU is included. The circuitry for aligning the operands causes the operand to be aligned by a lowest significant bit, wherein the circuitry for aligning the operand supplies an extension to the operand to allow the ALU to process different size operands.
|
申请公布号 |
US2005099841(A1) |
申请公布日期 |
2005.05.12 |
申请号 |
US20030726470 |
申请日期 |
2003.12.02 |
申请人 |
ADAPTEC, INC. |
发明人 |
MUKUND SHRIDHAR;GOPALAN MAHESH;KASHALKAR NEERAJ |
分类号 |
G06F9/30;G06F9/302;G06F9/315;G11C11/00;(IPC1-7):G11C11/00 |
主分类号 |
G06F9/30 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|