| 摘要 |
In a FET having a thin-film SOI layer, to prevent a parasitic resistance increase in source/drain regions. To realize an upheaved layer to be formed on the source/drain region without using a lithography process and without a fear of a short circuit. Element-isolation insulating films 7 , which are taller than a semiconductor layer 3 , are formed surrounding the island-shaped semiconductor layer (SOI layer) 3 , while gate electrodes 5 a , 8 a which are taller than the element-isolation insulating films 7 are formed on the semiconductor layer 3 . A polycrystalline silicon film 11 is deposited on the whole surface. Upheaved layers 11 a , 11 b which are shorter than the element-isolation insulating film 7 are formed on the source/drain regions 3 a , 3 b by chemical-mechanical polishing and etching back. Silicide layers 13 a to 13 c are formed on the gate electrode and on the upheaved layers. An interlayer insulating film 14 is formed, and a metal electrode 16 is formed.
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