| 摘要 |
PROBLEM TO BE SOLVED: To provide a logic synthetic method and a logic synthesizer which can reduce time and effort for analysis of a correction part and examination of contents of correction and facilitate further the correction of logic of a module even if large scale correction is needed at the time of logic design of a semiconductor integrated circuit. SOLUTION: Re-layering is attained after logic synthesis by leaving pins of a functional module as network information at the time of optimization of logic synthesis, and logic correction is easily attained after the logic synthesis by replacing a layered functional block, and at the same time suppression of area increment is also attained by specifying a module which leaves the pins. COPYRIGHT: (C)2005,JPO&NCIPI
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