发明名称 Cache control method and processor system
摘要 A cache control method controls data sharing conditions in a processor system having multi-level caches that are in an inclusion relationship. The cache control method indexes an upper level cache by a real address and indexes a lower level cache by a virtual address, and prevents a real address that is referred by a plurality of different virtual addresses from being registered a plurality of times within the same cache. A plurality of virtual addresses are registrable within the upper level cache, so as to relax the data sharing conditions.
申请公布号 US2005102473(A1) 申请公布日期 2005.05.12
申请号 US20040009466 申请日期 2004.12.13
申请人 FUJITSU LIMITED 发明人 SAKATA HIDEKI;NAKADA TATSUMI;ITO EIKI;NODOMI AKIRA
分类号 G06F12/00;G06F12/08;G06F12/10;(IPC1-7):G06F12/00 主分类号 G06F12/00
代理机构 代理人
主权项
地址