| 摘要 |
PROBLEM TO BE SOLVED: To provide a design method for a semiconductor integrated circuit allowing automatic correction of circuit information about a correction circuit into circuit information about a circuit wherein timing deterioration or wiring congestion is suppressed, along a cell layout of a mask layout design, in a short time. SOLUTION: When the circuit information about the correction circuit including a cell (an additional cell) of logic added according to a logic change generated after mask layout design completion of the semiconductor integrated circuit, information about arrangement coordinates of each cell on the mask layout design, and information about proper names of the additional cell and an auxiliary cell are inputted, a temporary proper name imparted to the additional cell is replaced with the proper name of the auxiliary cell of the same logic as the additional cell closest to gravity center coordinates of a cell group connected to the additional cell. COPYRIGHT: (C)2005,JPO&NCIPI
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