发明名称 METHOD OF DESIGNING POWER SUPPLY INTERCONNECTION
摘要 PROBLEM TO BE SOLVED: To provide a method of designing a power supply interconnection by which the voltage drop of a semiconductor chip can be predicted rapidly and accurately. SOLUTION: The method of designing a power supply interconnection structure for supplying power to a square-shaped semiconductor chip comprises a first step wherein the preparation of a power supply interconnection structure having an x-directional interconnection layer consisting of a plurality of parallel interconnections arranged in the y direction at an interconnection pitch p<SB>w</SB>, each having a resistance value of R<SB>int</SB>per unit length and being extended in the x direction, and a y-directional interconnection layer consisting of a plurality of parallel interconnections arranged in the x direction at the interconnection pitch p<SB>w</SB>, each having the resistance value of R<SB>int</SB>per unit length and being extended in the y direction is assumed; and a second step wherein a supply voltage drop V<SB>drop</SB>at the central point of the semiconductor chip is estimated using a formula (1), when supply voltage V<SB>dd</SB>is applied across each interconnection to supply power to the semiconductor chip. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005123365(A) 申请公布日期 2005.05.12
申请号 JP20030355971 申请日期 2003.10.16
申请人 NEC ELECTRONICS CORP 发明人 TAKAHASHI SOJI
分类号 G06F17/50;H01L21/82;(IPC1-7):H01L21/82 主分类号 G06F17/50
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