发明名称 Capacitance multiplier
摘要 A capacitance multiplier includes a self-biasing active load for generating a stable bias voltage without a separate current bias. In addition, the capacitance multiplier includes a cascode load within a multiplying section for increasing the output resistance and in turn the charging/discharging efficiency. Furthermore, the capacitance multiplier is implemented with a plurality of multiplying paths to reduce effects of noise for more stable generation of the multiplied capacitance.
申请公布号 US2005099221(A1) 申请公布日期 2005.05.12
申请号 US20040941357 申请日期 2004.09.15
申请人 KIM YOUNG-JIN;HWANG IN-CHUL;LEE HAN-IL;LEE JAE-HEON 发明人 KIM YOUNG-JIN;HWANG IN-CHUL;LEE HAN-IL;LEE JAE-HEON
分类号 H03H11/48;(IPC1-7):G06G7/16 主分类号 H03H11/48
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