A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.
申请公布号
WO2004112041(A3)
申请公布日期
2005.05.12
申请号
WO2004EP50867
申请日期
2004.05.19
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION;COMPAGNIE IBM FRANCE;HANSON, DAVID;FREDEMAN, GREGORY;GOLZ, JOHN;KIM, HOKI;PARRIES, PAUL
发明人
HANSON, DAVID;FREDEMAN, GREGORY;GOLZ, JOHN;KIM, HOKI;PARRIES, PAUL