发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGN METHOD THEREOF |
摘要 |
A design method of a logic circuit, capable of shortening the design period, is achieved by this invention. A semiconductor integrated circuit has a plurality of logic blocks each of which is constituted by a first logic circuit and a second logic circuit. Such semiconductor integrated circuit is designed in at least two steps: a first design step in which designing layout and timing verification are performed for a logic circuit including signal lines between the logic blocks and the first logic circuit; and a second design step in which layout and timing verification are performed for the second logic circuit in each logic block independently.
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申请公布号 |
WO2005043617(A1) |
申请公布日期 |
2005.05.12 |
申请号 |
WO2004JP16174 |
申请日期 |
2004.10.25 |
申请人 |
SEMICONDUCTOR ENERGY LABORATORY CO., LTD.;KATO, KIYOSHI |
发明人 |
KATO, KIYOSHI |
分类号 |
G06F17/50;(IPC1-7):H01L21/82;G01R31/28 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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