| 摘要 |
PROBLEM TO BE SOLVED: To provide a data transfer controller which can improve its data transfer speed and simplify its circuit. SOLUTION: An internal RAM 122 of a buffering mechanism 12 has a plurality of areas corresponding to the real addresses of a memory being the data transfer destination of image data, and can simultaneously execute writing into each area by a write control circuit 121 and reading therefrom by a read control circuit 124. The write control circuit 121, when writing the image data into the internal RAM 122, writes so that the address in the internal RAM 122 will correspond to the real address of the memory being the transfer destination of the image data. COPYRIGHT: (C)2005,JPO&NCIPI
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