发明名称 Method of generating a schematic driven layout for a hierarchical integrated circuit design
摘要 A method of generating a schematic driven layout for an integrated circuit design includes steps of: (a) receiving as input a representation of a integrated circuit design comprising a hierarchy of blocks; (b) selecting a block in the hierarchy of blocks that requires a physical design and that contains no missing components; (c) generating a physical design for the selected block so that the selected block is no longer a missing component of any other block; and (d) repeating steps (b) and (c) until a physical design has been generated for each block in the hierarchy of blocks.
申请公布号 US2005102645(A1) 申请公布日期 2005.05.12
申请号 US20030704922 申请日期 2003.11.10
申请人 SAUNDERS MICHAEL J.;MAUSE NORMAN E.;BREWSTER C. C. 发明人 SAUNDERS MICHAEL J.;MAUSE NORMAN E.;BREWSTER C. C.
分类号 G06F9/45;G06F9/455;G06F17/50;(IPC1-7):G06F9/455 主分类号 G06F9/45
代理机构 代理人
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