| 摘要 |
<p>An inverter type delay circuit, voltage-controlled oscillation circuit, and voltage-controlled delay circuit capable of realizing simplification of circuit configuration, reduction of an effect of power source noise, and reduction of jitter, wherein a delay circuit (100), voltage-controlled oscillation circuit, and voltage-controlled delay circuit comprised of a plurality of delay stages controlled in drive current in accordance with a bias voltage or a control voltage (Vcnt1, ..., Vcntj) and determined in delay time by the drive current, adding a change ( DELTA Vdd) of a power source voltage (Vdd) to the above bias voltage or control voltage (Vcnt1, ..., Vcntj) by a predetermined ratio (kc1, ..., kcj) and supplying a result of the addition (Vc1, ... Vcj) to the above delay stages to suppress the power source voltage dependencies of the delay times of the delay stages, or connecting by a predetermined ratio a plurality of delay stages having different power source voltage dependencies, for example, power source voltage dependencies of opposite delay times, to suppress the power source voltage dependencies of delay times of the delay stages are realized. <IMAGE></p> |
