发明名称 |
Hardware semaphores for a multi-processor system within a shared memory architecture |
摘要 |
A circuit generally comprising a memory element and a controller. The memory element may define a semaphore allocatable to a resource. The controller may be configured to (i) present a granted status in response to a processor reading a first address while the semaphore has a free status, (ii) set the semaphore to a busy status in response to presenting the granted status, and (iii) present the busy status in response to the processor reading the first address while the semaphore has the busy status.
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申请公布号 |
US6892258(B1) |
申请公布日期 |
2005.05.10 |
申请号 |
US20010015076 |
申请日期 |
2001.10.26 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
WILLIAMS KALVIN E.;HOLCROFT JOHN S.;LANE CHRISTOPHER J. |
分类号 |
G06F13/00;G06F13/14;G06F13/16;(IPC1-7):G06F13/14 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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