发明名称 |
Test structure of DRAM |
摘要 |
A test structure of a DRAM array includes a substrate. A transistor is formed on the substrate and has a first region and a second region as source/drain regions thereof. A deep trench capacitor is formed adjacent to the transistor and has a first width. A shallow trench isolation is formed in a top portion of the deep trench capacitor and has a second width. The second width is substantially shorter than the first one. A third region is formed adjacent to the deep trench capacitor. A first contact is formed on the substrate and contacts with the first region. A second contact is formed on the substrate and contacts with the third region.
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申请公布号 |
US6891216(B1) |
申请公布日期 |
2005.05.10 |
申请号 |
US20030664163 |
申请日期 |
2003.09.17 |
申请人 |
NANYA TECHNOLOGY CORPORATION |
发明人 |
HUANG CHIEN-CHANG;WU TIE-JIANG;HUANG CHIN-LING;TING YU-WEI;JIANG BO-CHING |
分类号 |
H01L21/334;H01L21/8242;H01L23/544;H01L27/108;(IPC1-7):H01L31/119;H01L29/94;H01L29/76 |
主分类号 |
H01L21/334 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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