发明名称 Arrangement for testing a network device by interfacing a low speed emulation system with high speed CPU
摘要 A system is provided for delaying a ready signal from an emulation system, configured for emulating a network device, to a central processing unit (CPU) for initiating an access cycle of the CPU. The system includes an emulation system and a central processing unit (CPU). The emulation system is configured for operating according to an emulation clock having a maximum speed substantially less than a prescribed operating speed of the CPU. The emulation system includes programmable device configured for receiving a ready signal from the emulation system, delaying the ready signal based on the emulation clock, and sending the delayed ready signal to the CPU based on the emulation clock. The delayed ready signal enables the emulation system to complete the access cycle of the CPU prior to the CPU initiating processing of subsequent instructions.
申请公布号 US6892174(B1) 申请公布日期 2005.05.10
申请号 US20010847427 申请日期 2001.05.03
申请人 ADVANCED MICRO DEVICES, INC. 发明人 GASPAR HARAND
分类号 G06F9/455;G06F11/26;(IPC1-7):G06F9/455 主分类号 G06F9/455
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