发明名称 |
Fully hidden refresh dynamic random access memory |
摘要 |
Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.
|
申请公布号 |
US6891770(B2) |
申请公布日期 |
2005.05.10 |
申请号 |
US20040920421 |
申请日期 |
2004.08.18 |
申请人 |
RENESAS TECHNOLOGY CORP. |
发明人 |
TAKATSUKA TAKAFUMI;SATO HIROTOSHI;TSUKUDE MASAKI |
分类号 |
G11C11/403;G11C8/18;G11C11/406;G11C11/408;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/403 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|