| 摘要 |
Semiconductor devices are tested simultaneously by using an instrument of simple structure. Latch circuits (13a to 13d) latch the output signals outputted from DUTs (12a to 12d) into which the same test signal (test) is inputted. A P-S converter circuit (15) sequentially outputs expectation value signals (exp) representing the expectation values of the signals to be outputted from the DUTs (12a to 12d) in response to the test signal (test) and latch signals (Dout1 to Dout4) during a latch period. An encoder circuit (16) compares the expectation signals (exp) with the latch signals (Dout1 to Dout4). If the expectation value signal (exp) does not agree with the latch signals (Dout1 to Dout4), the latch signals (Dout1 to Dout4) outputted from the P-S converter circuit (15) and the expectation value signals (exp) are stored in a memory (18). A judgment circuit (19) judges from the latch signals (Dout1 to Dout4) and the expectation value signals (exp) whether or not the DUTs (12a to 12d) are defective.
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