发明名称 DUAL LOOP SENSING SCHEME FOR RESISTIVE MEMORY ELEMENTS
摘要 According to one aspect of the present invention, MRAM cell logic state is sensed by configuring an memory cell so as to form a sensing voltage across the cell that is related to a resistance of the cell. The sensing voltage is applied to an input of a transconductance amplifier, which outputs a sensing current related to the sensing voltage.
申请公布号 KR20050042482(A) 申请公布日期 2005.05.09
申请号 KR20057002830 申请日期 2005.02.18
申请人 MICRON TECHNOLOGY, INC. 发明人 BAKER, R., JACOB
分类号 G11C11/15;G11C7/06;G11C11/16;(IPC1-7):G11C11/15 主分类号 G11C11/15
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