RANDOM ACCESS MEMORY WITH DATA STROBE LOCKING CIRCUIT

摘要

A random access memory comprises a latching circuit (106, 110) configured to receive a first signal (104) and provide a second signal (116) corresponding to the first signal to latch data signals into the random access memory. The random access memory comprises a logic circuit (112) configured to provide a first response (119) after a predetermined number of the data signals have been latched into the random access memory by the second signal. The latching circuit is configured to receive the first response and lock the second signal to a logic level based on the first signal and the first response to prevent inadvertent latching of other data signals.