发明名称 |
A DIGITAL PULSE WIDTH MODULATOR |
摘要 |
A DPWM (1) has a delay lock loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each of eight delay cells (35). A multiplexer (5) selects one of the delay cell outputs at any one time. This allows the DPWM (1) to have eight times the resolution which would otherwise be achieved with the same input clock. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output. |
申请公布号 |
WO2005011118(A3) |
申请公布日期 |
2005.05.06 |
申请号 |
WO2004IE00101 |
申请日期 |
2004.07.26 |
申请人 |
UNIVERSITY OF LIMERICK;O'MALLEY, EAMON;RINNE, KARL |
发明人 |
O'MALLEY, EAMON;RINNE, KARL |
分类号 |
H02M3/335;H03K5/00;H03K5/13;H03K7/08;H03L7/081 |
主分类号 |
H02M3/335 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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