SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR REFRESHING THE SAME

摘要

[PROBLEMS] To provide a DRAM wherein a refresh operation can be inserted between ordinary access operations and wherein the internal cycle time can be set to be longer than a half of the external cycle time. [MEANS FOR SOLVING PROGRAMS] An address selector (18) selects an access row address signal (ERA) or a refresh row address signal (RRA). A row decoder control circuit (16) selects, in response to a selected row address signal (RA), one of blocks into which the memory cell array is divided, and causes a row decoder circuit (22) to select a word line. If an operation is initiated in any one of the blocks, then a busy signal (/BUSY) is activated to inhibit the address selector (18) from performing any selection. When the operation is terminated, the busy signal (/BUSY) is deactivated to release the inhibition of the address selector (18). Accordingly, a precedently inputted row address signal (ERA or RRA) is given a higher priority, and a subsequently inputted row address signal (RRA or ERA) is caused to wait until a termination of the precedent operation.