发明名称 |
ECHO CLOCK ON MEMORY SYSTEM HAVING WAIT INFORMATION |
摘要 |
A method and a circuit configuration for implementing a double data rate feature in a memory device capable of operating in a variable latency mode. The memory device may utilize a WAIT_DQS signal that combines functionality of a WAIT signal indicating when valid data is present on a data bus in Read cycle and the memory is ready to accept data in Write cycle, and a data strobe (DQS) signal. |
申请公布号 |
WO2005041055(A2) |
申请公布日期 |
2005.05.06 |
申请号 |
WO2004EP10411 |
申请日期 |
2004.09.16 |
申请人 |
INFINEON TECHNOLOGIES AG;OH, JONG-HOON |
发明人 |
OH, JONG-HOON |
分类号 |
G06F13/16;G06F13/42;G11C7/00;G11C7/10;G11C8/00 |
主分类号 |
G06F13/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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