发明名称 |
Multiplier-divider circuit for a PFC controller |
摘要 |
The present invention introduces an integrated analog multiplier-divider circuit. The multiplier-divider block according to the present invention is ideal for use in the power factor correction (PFC) controllers of many switch-mode power supplies. The analog multiplier-divider according to the present invention is built from CMOS devices. Because of this, it has many advantages over prior-art multiplier-dividers. One important advantage is that the die-size and the cost can be reduced. Another important advantage of the multiplier-divider according to the present invention is substantially reduced temperature dependence.
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申请公布号 |
US2005093528(A1) |
申请公布日期 |
2005.05.05 |
申请号 |
US20030700787 |
申请日期 |
2003.11.03 |
申请人 |
YANG TA-YUNG;LIN SONG-YI;HSUEH CHENG-CHI |
发明人 |
YANG TA-YUNG;LIN SONG-YI;HSUEH CHENG-CHI |
分类号 |
G05F1/40;H02M1/00;H02M1/42;(IPC1-7):G05F1/40 |
主分类号 |
G05F1/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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