发明名称 Memory module with registers
摘要 Pairs of registers with reduced pins are disposed to overlap on front and back surfaces of a memory module. An input signal INS is transferred through the registers in series in a daisy chain fashion to avoid divergence of the input signal INS for preserved signal integrity. Each register buffers the input signal INS to memory banks disposed closely to sides of the register for reduced wiring area.
申请公布号 US2005097264(A1) 申请公布日期 2005.05.05
申请号 US20040975810 申请日期 2004.10.27
申请人 PARK KWANG-SOO;CHO JEONG-HYEON;SO BYUNG-SE;LEE JUNG-JOON;YUN YOUNG;KIM KWANG-SEOP 发明人 PARK KWANG-SOO;CHO JEONG-HYEON;SO BYUNG-SE;LEE JUNG-JOON;YUN YOUNG;KIM KWANG-SEOP
分类号 G06F12/00;G06F12/06;G06F13/16;G11C5/00;H01L23/50;(IPC1-7):G06F12/00 主分类号 G06F12/00
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